“ACS Appl. Mater. Interfaces”: The Influence of Parasitic Capacitance on the Dynamic Performance of Electrolyte-Gated Poly(3-hexylthiophene) Transistors Printed by Aerosol Jet Printing at Gate Voltages Below 2 V

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Equipment Parameters

I. Core Research Summary

This study employs the Optomec aerosol jet printing system to fabricate the P3HT semiconductor layer, the ionic‑gel gate dielectric, and the PEDOT:PSS gate electrode. Source–drain gold electrodes are patterned via photolithography, enabling the construction of polymer‑electrolyte‑gate transistors (EGTs) and inverter circuits driven at voltages below 2 V. The key findings and results are summarized as follows:
  • A huge discrepancy between theoretical and measured frequencies

According to the carrier transport equation, a 2.5-μm short-channel device can theoretically achieve a switching frequency of up to 10 MHz; however, measured values remain in the kHz range, demonstrating that device speed is not limited by semiconductor mobility, with parasitic capacitance serving as the dominant limiting factor.

  • Complete verification of the influence patterns of parasitic capacitance

The cutoff frequency is inversely proportional to the drain electrode area and independent of the channel length; under the condition of a fixed total electrode width, reducing the drain electrode size and enlarging the source electrode can significantly decrease the RC relaxation time, suppress voltage spikes, and enhance the response speed.

  • Optimal geometric structure enables 10 kHz high-speed devices.

With a channel length L = 2.5 μm, channel width W = 50 μm, and electrode width a = 2.5 μm, the device achieves a cutoff frequency of 10 kHz, maintains an output voltage exceeding 90% of the input amplitude, and exhibits optimal dynamic bandwidth performance.

  • Aerosol Multilayer Integrated Molding Process

The three functional layers—semiconductor, ionic gel, and conductive gate—are all fabricated via aerosol jet printing, eliminating the need for vacuum evaporation. With broad ink compatibility, this approach enables the scalable fabrication of low-voltage transistors on both flexible and rigid substrates.

  • The device exhibits excellent static performance.

P3HT exhibits a hole mobility of approximately 1 cm²/V·s, an on/off ratio of 10⁵, an off-state leakage current as low as 100 pA, and operates at a supply voltage of only −1 V, making it well suited for lightweight electronic systems powered by thin-film batteries.

II. Core Technological Advantages of Device Fabrication via Aerosol Jet Printing

(1) Complete Layer-by-Layer Printing Process for Aerosols

  • Au source and drain electrodes are fabricated by lithography on a silicon substrate.
  • Ultrasonic atomization of P3HT–chloroform ink enables aerosol jet printing of active channels.
  • Print PS-PMMA ionic gel as a high-capacitance gate dielectric;
  • Aerosol-printed PEDOT:PSS conductive gate and load resistor;
  • Low-temperature curing of components in a nitrogen glove box.

(II) Five Unique Process Advantages (Compared with Spin Coating / Inkjet Printing)

  • Direct Writing of Multilayer Functional Materials in a Single Step

Ink formulations spanning three vastly different material classes—organic semiconductors, ionic gels, and conductive polymers—can be deposited using a single device, eliminating the need to switch between multiple processing systems and thereby streamlining fully printed circuit‑fabrication lines.

  • Non-contact, non-destructive deposition

The ionic gel exhibits a soft texture, and spin coating readily wets and removes the underlying P3HT thin film. Aerosol droplets spread gently without disrupting the interface of the already formed active layer.

  • Micrometer-scale pattern controllability

CAD‑customized gate and resistor patterns, with high precision tailored to short‑channel micron‑scale devices, meet the requirements of high‑speed transistor miniaturization.

  • Compatible with wide-viscosity inks

Low-concentration P3HT dilute solutions, viscous ionic gels, and highly conductive PEDOT slurries can all be stably atomized, with no risk of nozzle clogging.

  • Compatible with flexible, scalable substrates

The process operates at mild temperatures, ensuring no thermal damage to PI and PET flexible films, and is compatible with high-speed, continuous roll-to-roll printing of logic arrays.

III. Key Technological Innovations of This Study

Innovation 1: Clearly identify parasitic capacitance as the core bottleneck limiting the speed of printed EGT.

Previous studies have assumed that transistor speed is determined by semiconductor carrier mobility. In this work, through controlled-variable experiments, we overturn this conventional wisdom and demonstrate that the parasitic capacitance arising from gate–drain overlap introduces RC delays that significantly slow signal response, thereby pointing to a new avenue for optimizing high-speed printed transistors.

Innovation 2: Establishing Quantitative Laws for Device Geometric Dimension Optimization

Three key structural relationships are clarified: (1) the cutoff frequency is linearly negatively correlated with the drain electrode width; (2) channel length has virtually no impact on dynamic performance; and (3) when the total electrode width remains constant, a structure featuring a narrow drain and a wide source is optimal. Standardized layout design guidelines are also provided.

Innovation 3: Complete Process for Aerosol-Based All-Ion Gel-Grid Dielectric Technology

Aerosol‑based uniform deposition yields an ultrathin, high‑capacitance ionic gel (with a surface capacitance on the order of 10 μF/cm²), which forms a nanoscale electric double layer, enabling ultra‑low gate‑voltage operation below 2 V and eliminating the constraints imposed by high‑voltage power supplies.

Innovation 4: A Balanced Solution That Simultaneously Optimizes Static Performance and Dynamic Bandwidth

By reducing the leakage electrode to lower parasitic capacitance while maintaining a large width-to-length ratio (W/L), we ensure low on‑resistance and high output swing, thereby resolving the trade‑off between increased speed and degraded output performance.

Innovation 5: Aerosol-Integrated Printing Inverter Unit

Active layer, gate dielectric, and load resistor are simultaneously fabricated via aerosol deposition, enabling the fabrication of a complete printed logic unit that can be directly extended to oscillators and sensor readout circuits.

IV. Existing Challenges in Processes and Devices, and Proposed Solutions for Overcoming Them

Challenge 1: The gate and drain overlap over a very large area, resulting in substantial parasitic capacitance, which leads to significant signal delay and severe voltage spikes.

✅ Breakthrough: Optimized layout, minimized electrode width, fixed total source‑electrode width, significantly reduced Cpar and D, shortened RC relaxation time, and increased the cutoff frequency to 10 kHz.

Challenge 2: Simply shortening the channel cannot increase circuit speed, rendering conventional device‑optimization approaches ineffective.

✅ Breakthrough: Abandoning the approach of merely scaling the channel, we prioritize optimizing the electrode geometry to address speed bottlenecks at the parasitic‑parameter level.

Challenge 3: Thick ionogel films further increase the gate–drain overlap capacitance.

✅ Breakthrough: Aerosol-based multilayer thin-film printing enables precise control of gel film thickness, reducing vertical overlap area while maintaining high capacitance and low-voltage performance.

Challenge 4: A too-small channel width-to-length ratio increases on-resistance and causes output voltage droop.

✅Breakthrough: By maintaining a large channel width of W = 50 μm and solely reducing the electrode dimensions, we achieve both high speed and a large output swing.

Challenge 5: In aerosol-based multilayer printing, interlayer miscibility is prone to occur, leading to increased interfacial leakage.

✅ Breakthrough: After each layer is printed, it undergoes segmented low-temperature drying, allowing the solvent to fully evaporate before depositing the next layer, thereby isolating the interface between P3HT and the ionic gel.

V. Future Industrial Application Scenarios

1. Flexible Printed Logic Circuits and Ring Oscillators

A 10 kHz response speed meets the requirements of low‑frequency digital circuits, while all‑gasoline‑based low‑voltage transistors are employed in flexible display drivers and RFID tag logic units, with low‑voltage operation compatible with miniature thin‑film batteries.

2. Wearable physiological sensing readout chip

Ultra-low operating voltage and a lightweight, flexible substrate are employed in ECG and pressure-sensing array signal acquisition circuits to enable rapid response to faint physiological signals.

3. Electronic Fabrics and Textile Electronics Circuits

Aerosol‑direct‑write low‑voltage transistor on fabric surfaces, with touch‑sensitive and temperature‑sensing active circuits for smart apparel, all integrated into a lightweight design without rigid chips.

4. Indoor Low-Light Micro Photovoltaic Auxiliary Control Circuit

Organic photovoltaics paired with printed transistors of the same system constitute a fully solution‑processed, low‑voltage, self‑powered system for passive IoT sensing nodes.

5. Large-area flexible sensor array

Strain sensing, optoelectronic sensing with active matrix, large-area batch fabrication of aerosols, low power consumption, and bendable—suitable… Equipped with industrial flexible monitoring devices.
Image and Text Guide

Figure 1. Aerosol-jet-printed inverter. (a and b) Side and top views of an EGT inverter with a P3HT semiconductor channel and PEDOT:PSS resistive load. Electrodes are patterned on a Si/SiO₂ (300 nm) wafer using photolithography, while the remaining layers are deposited via aerosol-jet printing. Parasitic capacitance arises from the overlapping regions of the ionic gel on the source and drain electrodes. (c) Geometry of the channel and electrodes, showing channel length (L), channel width (W), and electrode width (a); unless otherwise specified, the same source/drain electrode area is used for all configurations. (d) The thickness of the deposited P3HT film is 30 nm. (e) Ionic gel printed on the surface of the P3HT film; (f) PEDOT:PSS gate material formed by aerosol-jet printing over the ionic gel/P3HT film. The channel length is 25 μm, and the electrode width is 5 μm.

Figure 2. Quasi‑static measurement results for a P3HT EGT with dimensions W = 500 μm, L = 25 μm, and a = 5 μm. (a) Transfer curve of the aerosol‑jet‑printed P3HT EGT under VD = −0.5 V, Vt = −0.34 V, μ = 1.2 cm²/(V·s), with 5 × 10⁵ ON/OFF switching cycles and an off‑state current of 100 pA; (b) Output characteristic curve of the P3HT EGT; (c) Step response of the inverter built from this device; (d) Quasi‑static gain curve of the inverter, showing Vout/VDD = 0.98. Scan rate: 50 mV/s.

Figure 3 shows the dynamic performance of an EGT device with dimensions W = 50 μm, L = 2.5 μm, and a = 2.5 μm under different conditions when VDD = −1 V: (a) the low‑frequency quasi‑dynamic response to a 10 Hz square‑wave input (output voltage Vout DD = 0.9); (b) the dynamic response to a 5 kHz square‑wave input (output voltage Vout DD = 0.87); and (c) the dynamic response at a frequency of 10 kHz. The figure labels the pulse amplitude (Vspike), pulse duration (tspike), and the ideal response time (tideal). At the cutoff frequency (fcut-off), the actual pulse duration equals the ideal response time; here, the pulse duration and the normalized pulse amplitude (VVspike DD) are 20.9 μs and 1.42 μs, respectively.

Figure 4. Geometric dependence of the cutoff frequency (f_cut-off). (a) f_cut-off as a function of L, with W held constant; (b) f_cut-off as a function of W, with L held constant; (c) f_cut-off as a function of W, with both W and L held constant. Error bars represent one standard deviation.

Figure 5. Relationship between the cutoff frequency and the source and drain electrode widths. The inset shows a top‑view of the channel and electrode structure, including the source width (aS) and the drain width (aD). The channel width (W), channel length (L), and total electrode width (aD + aS = aT) are fixed at 50 µm, 2.5 µm, and 15 µm, respectively; the drain width (aD) is varied from 2.5 to 12.5 µm. The results indicate that, when the drain width (aD) is small, a larger source width (aS) yields a higher cutoff frequency (fcut-off). Error bars represent one standard deviation.

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