I. Core Research Summary

• Extremely low gate‑voltage hysteresis and zero drift of circuit signals.

The top-gate device exhibits a hysteresis of only 0.23 V, while the flexible-substrate device shows a hysteresis of approximately 0.5 V—both significantly lower than that of conventional SiO₂‑based bottom-gate devices, which can exhibit hysteresis as high as 35 V. Moreover, after prolonged bias stress and seven weeks of ambient‑air storage, the threshold voltage remains virtually unchanged, completely eliminating signal distortion caused by interface charge traps.

• Excellent comprehensive electrical performance

The carrier mobility reaches as high as 16.1 cm²/V·s, the on–off ratio can attain 6×10⁴, and the subthreshold swing is exceptionally favorable. Complete saturation output characteristics are achieved even at low gate voltages, without the need for high‑temperature vacuum post‑treatment.

• Ultra-strong mechanical flexibility and durability

With an ultra‑small bending radius of 1 mm, the transfer curve remains virtually unchanged after 1,000 consecutive bends; only at an extreme bend radius of 0.5 mm do microcracks appear in the silver electrodes, making it well suited for foldable and stretchable flexible devices.

• Single-device, fully in-situ printing simplifies the production line.

All four functional layers are integrated into a single aerosol‑based fabrication process, eliminating the need for lithography, spin coating, and evaporation deposition steps. Coupled with an in‑situ toluene‑cleaning protocol for carbon nanotubes, the process avoids the necessity of removing samples for wet‑chemical soaking, thereby significantly enhancing automation.

• Hydrophobic Self-Passivation Mechanism of the Gate Dielectric

After film formation, the pMSSQ component in XDI‑DCS spontaneously rises to the surface, creating a hydrophobic top layer that isolates water vapor and hydroxyl traps, thereby suppressing hysteresis at its source without the need for an additional encapsulating protective layer.

II. Core Operating Principle of Aerosol Spraying and Its Unique Process Advantages

(1) Complete In-Situ Printing Process

• Base cleaning + oxygen plasma activation; for silicon substrates, additional PLL‑mediated hydrophilic modification.
• The sample is fixed on a printing stage throughout the entire process, with in-situ aerosol printing of the silver source and drain, followed by sintering on a 150°C heated stage.
• In situ printing of semiconductor single-walled carbon nanotube channels, with the substrate directly rinsed with toluene to remove the dispersant.
• Layered aerosol printing of an XDI-DCS composite gate dielectric, followed by segmented low-temperature curing;
• In-situ printing of top-gate silver electrodes, with the entire process performed without removing the substrate.

(II) Five Core Process Advantages (Compared with Inkjet, Screen Printing, and Spin Coating)

• Fully integrated in-situ molding, no wafer transfer required.

Most “all‑printed” TFTs on the market still combine lithography with spin‑coated dielectrics; in this approach, all four layers are deposited via aerosol deposition, with the sample remaining stationary throughout the process, thereby eliminating alignment errors and contamination risks and significantly boosting yield.

• Ultra-wide ink compatibility—single equipment handles metal, semiconductor, and insulator applications.

It is simultaneously compatible with silver‑nanoparticle conductive ink, high‑purity carbon‑nanotube dispersions, and polymer‑based dielectric inks, eliminating the need to replace the atomization module and halving the capital investment in production equipment.

• Sheath‑gas anti‑clogging + non‑contact deposition, compatible with ultra‑thin flexible films.

Coaxial nitrogen‑sheath‑gas‑isolated nozzle ensures clog‑free printing even during extended runs; the nozzle–substrate gap is adjustable, and the ultra‑thin 25 µm Kapton film remains free from compression‑induced wrinkling or damage.

• Precision area printing, significant ink savings

The medium is printed only on the region above the channel, eliminating the need for full‑area spin coating; this boosts material utilization by several fold and makes it well suited for the mass production of high‑cost carbon nanomaterials.

• Low-temperature, mild processing, with a maximum treatment temperature of 150°C.

The entire process avoids ultra-high-temperature steps, ensuring that PET, PI, and paper‑based thermal substrates remain intact, making it well suited for low‑cost, disposable flexible electronics.

III. Five Key Technological Innovations

Innovation 1: XDI-DCS hydrophobic self-passivating gate dielectric, eliminating charge-trap hysteresis.

Innovation 2: In-situ platen cleaning process, eliminating the need for an external wet‑process step.

Innovation 3: The top-gate device architecture significantly reduces the threshold voltage.

Innovative nano‑composite thin‑film system with 4,1000-fold bending stability

Innovation 5: Maskless micrometer-scale direct patterning, compatible with rigid and dual substrates.

IV. Existing Process Challenges and Corresponding Solutions for Overcoming Them

Challenge 1: The conventional SiO₂ bottom-gate interface harbors numerous hydroxyl traps, resulting in hysteresis as high as several tens of volts.

Challenge 2: Residual dispersants on the surface of carbon nanotubes reduce mobility.

Challenge 3: Mutual solubility of multi-layer inks leading to interfacial delamination and leakage current.

Challenge 4: Thin silver electrodes are prone to cracking under extreme bending, leading to device failure.

Challenge 5: Large alignment deviations in multi‑device composite processes and batch-to-batch variability.

V. Future Diversified Industrial Application Scenarios

1. Flexible Electronic Skin and Medical Wearable Sensors

2. Foldable display, electronic paper drive backplane

3. Single-use paper IoT RFID tag

4. Lightweight Measurement and Control Chip for Extreme Environments

5. Fabric-based Intelligent Touch-Control Electronics

Figure 1. All-printed, flexible carbon nanotube thin-film transistors (CNT‑TFTs) with no hysteresis. a) Schematic illustrating the fabrication process of a top‑gate CNT‑TFT, comprising: (I) substrate preparation via cleaning, plasma treatment, and poly‑L‑lysine (PLL) modification; (II) source/drain electrode deposition by spray printing; (III) carbon nanotube film channel; (IV) gate dielectric layer; and (V) gate electrode. b) Optical image of a printed CNT‑TFT array on a silicon wafer. c) Optical image of the top‑gate CNT‑TFT after all layers have been printed. d) Photograph of a flexible CNT‑TFT and logic circuitry on a hexagonal boron nitride (h‑BN) substrate. e) Scanning electron microscope (SEM) image of the top‑gate CNT‑TFT on h‑BN, clearly showing four printed layers, including the underlying carbon nanotube network. f) SEM image of the semiconducting carbon nanotube network in the CNT‑TFT channel region, with a uniform distribution and a density of approximately 40 nanotubes µm⁻². g) SEM image of the printed silver contact electrodes after annealing at 150°C for 1 hour, where silver nanoparticles have aggregated to enhance electrical conductivity.

Figure 2. Performance comparison of all-printed top-gate and bottom-gate carbon nanotube transistors on a rigid substrate. a) Schematic of a top-gate carbon nanotube transistor, with layers vertically separated for clarity; b) Optical image of a representative top-gate device, in which the gate overlaps the source and drain electrodes; c) Subthreshold characteristics (Id–Vgs) of the top-gate device (L = 120 µm, W = 200 µm) under both forward and reverse scan conditions; at a gate voltage Vds = −1 V, hysteresis is negligible (~0.23 V), and the threshold voltage is −12.5 V; d) Subthreshold characteristics of the same device at different Vds values; e) Output characteristics (Id–Vds) of the same device, demonstrating good saturation behavior at low Vds; f) Schematic of a bottom-gate carbon nanotube transistor, with layers vertically separated; g) Optical image of a representative bottom-gate device, where the gate overlaps the S/D electrodes; h) Subthreshold characteristics (Id–Vgs) of the bottom-gate device (L = 120 µm, W = 200 µm) under both forward and reverse scan conditions; hysteresis is small (2.4 V), and the threshold voltage is 2.3 V; i) Subthreshold characteristics of the same device at various Vds values; j) Output characteristics (Id–Vds) of the same device, indicating that its contacts exhibit good linear behavior.

Figure 3. Stress testing and the influence of substrate‑induced dielectric charges on carbon nanotube field‑effect transistors (CNT‑TFTs). a) Stress‑test results for a printed xdie‑dcs dielectric layer under a gate voltage Vds = −1 V, showing transfer curves across different scan ranges from ±10 to ±40 V; the inset illustrates the extracted threshold voltages (Vth) for both forward and reverse scan directions. b, c) Hysteresis and threshold‑voltage (Vth) stability of printed top‑gate CNT‑FET devices in ambient air, with data collected at multiple time points over a 7‑week period; each data point represents the average of 3–5 devices. d) Subthreshold characteristics (Id–VTG) of a top‑gate CNT‑FET (length L = 120 µm, width W = 200 µm) before and after applying a negative gate‑voltage sweep (Id–VBG): the initial Id–VTG hysteresis is only 0.3 V; however, upon performing a negative scan from the substrate gate (0 → −40 V → 0), the ion current (ION) in the Id–VTG curve drops sharply, increasing the hysteresis to 2.4 V and shifting the threshold voltage to −21.6 V. Over time, the Id–VTG performance partially recovers, yet the hysteresis cannot be fully eliminated, leaving a final hysteresis of 1.2 V and a threshold voltage of −2.5 V. e) The same device after a positive scan applied from the substrate gate (0 → +40 V → 0) reveals subthreshold characteristics (Id–VBG) that differ markedly from those observed under negative scanning: here, ION increases significantly, the hysteresis ultimately decreases to 0.8 V, and the threshold voltage gradually rises to 6.9 V after approximately one hour.

Figure 4. Performance and bending test results of all-printed carbon nanotube transistors (CNT‑TFTs) on flexible substrates. a) Micrograph of a uniformly printed, top‑gate CNT‑TFT array on a polyimide film (25 µm thick); b) SEM image of the silver gate electrode after 1,000 bending cycles (curvature radius 1 mm), with no cracks or delamination observed on the electrode surface; c) SEM image of the same electrode after multiple bending cycles (curvature radius 0.5 mm), showing localized delamination and cracking; d) Subthreshold transfer characteristics (Id–Vgs) of a representative top‑gate CNT‑TFT device (length 120 µm, width 200 µm), with negligible hysteresis between forward and reverse sweeps (~0.5 V) and a threshold voltage of −1.9 V; e) Subthreshold characteristics of the same device; f) Output characteristics; g) Subthreshold transfer curves for the device after varying numbers of bending cycles (curvature radius 1 mm); h) Transfer curves at different bending curvature radii. The polyimide film thickness is 25 µm. Inset in (g): Micrograph of the printed device substrate wrapped around a cylinder with a 1-mm curvature radius. After 1,000 bending cycles, the performance degradation at a 1-mm curvature radius is negligible; i) Relationship between tensile strain on the surface of the printed dielectric layer and the bending curvature radius on a flexible substrate. Tensile strain increases with substrate thickness and decreases with increasing bending radius; j) Strain distribution in the bent dielectric film on a Kapton substrate (25 µm thick), calculated using a finite-element model: when the film is bent with a smaller radius, the tensile strain on its surface—specifically, on the top side of the xdie-dcs film—is higher.

Figure 5. Comparison of the performance (hysteresis and threshold voltage) of fully printed flexible CNT‑TFTs with that of printed CNT‑TFTs reported in other studies. The asterisk indicates the performance of the printed flexible device presented in this work, which exhibits a hysteresis of approximately 0.5 V and a threshold voltage of −1.9 V. The figure shows four different dielectric materials (denoted by oval symbols): PVP/pMSSQ or xdic.sq (red), barium titanate/PMMA (blue), ionic gel (orange), and a polytetrafluoroethylene–aramid composite (cyan). The dielectric used in reference [39] was prepared by spin coating, whereas the devices reported in references [2] and [6] were fabricated using a partially printed approach. When data are not explicitly provided, values extracted from the cited literature are estimated based on the reported curves.