I. Core Research Summary

• In-situ integrated four-layer aerosol sensing stack structure for heat sinks

The entire sensor array is fabricated via aerosol jet printing, comprising four layers: a bottom electrode, an NTC thermistor layer, and a top electrode, with the lead-out wires routed from the lower layer. The monitoring area on a single chip measures just 9 × 22 mm; electrode line widths range from 60 to 80 μm, pixel dimensions are 60 × 60 μm, and the ultrathin functional layer introduces no additional thermal resistance.

• High-sensitivity NTC thermistor sensing performance

The thermistor exhibits an excellent negative temperature coefficient, with a TCR of less than −3.8%/°C at 20°C and remaining at −2.2%/°C even at 100°C. Its per‑pixel power consumption is only 2 μW, resulting in negligible self‑heating, and it achieves a temperature‑measurement readout frame rate of 20 Hz.

• Millisecond-level kernel hotspot detection capability

Equipped with an Intel i9 eight-core processor, real-world testing shows that under single-core stress, localized temperature rises can be detected within 50 milliseconds. Under sustained heavy loads, the hotspot distribution clearly distinguishes all eight independent cores, generating a unique thermal fingerprint map.

• Low-Interference Passive Matrix Readout Scheme

A self-developed zero-potential scanning drive circuit eliminates row‑column crosstalk; a universal fourth‑order polynomial correction is employed, enabling uniform temperature‑measurement accuracy across all pixels with a single baseline scaling, eliminating the need for per‑pixel calibration.

• Without compromising the original cooling system.

With a base insulating layer of only 5 μm polyimide, the thermal resistance increase is extremely low; it enables long-term online monitoring without opening the device, replacing intermittent infrared thermography, and can acquire CPU thermal‑distribution data in real time, 24/7, for hardware health assessment and malicious‑code detection.

II. Complete Preparation Process Flow and Core Process Advantages of Aerosol Spraying

(1) Complete Preparation Process for the Radiator Sensor Array

• Polishing and cleaning of the aluminum water-cooled heat sink, followed by spin coating a 5 μm ultra-thin PI insulating film, which is then cured at 350°C to achieve electrical isolation.
• Optomec’s aerosol‑jet equipment uses ultrasonic atomization to print wide‑format conductive traces with silver nanoparticle‑based aqueous inks, followed by pulsed‑light sintering to enhance electrical conductivity.
• Replace the small-diameter nozzle, print a 60 μm‑thick, fine‑grained bottom electrode layer, and perform photopolymerization again.
• Diluted and modified NTC thermosensitive ink is applied in a continuous serpentine pattern via pneumatic atomization to form the thermosensitive sensing layer, which is then uniformly cured in a 120°C oven for an extended period.
• The top electrode and the bottom electrode are vertically intersected via aerosol printing, followed by low-temperature annealing to relieve internal stresses in the thin film.
• Paired with an FFC flexible cable and a dedicated readout board, the system is mounted directly onto the bare CPU to perform full‑system temperature testing.

(II) Five Core Processes (Comparison of Lithography, Screen Printing, and Flexible Film Lamination)

• Direct conformal printing of irregular-shaped metal heat sinks

Eliminates the need for separate PI film transfer; sensor circuits are directly formed on the surface of the metal heat‑dissipating component, resulting in superior conformability and eliminating the air‑gap thermal barrier between the film and the heat sink.

• Micron-level high-precision multi-layer precise overprinting

Aerosol-based CNC positioning enables multi-layer stacking, while electrode cross‑pixel alignment achieves extremely low misalignment, yielding a high‑density thermopile array of nearly 400 pixels—something that cannot be realized with screen printing on a micro‑pixel grid.

• Ultra-thin, low-resistance film that virtually does not impede heat dissipation.

The single-layer conductive film is only 3–4 μm thick, with an insulating layer of 5 μm; the overall additional thermal resistance is far lower than that of commercially available flexible temperature‑sensing films, so it does not exacerbate CPU temperature rise.

• Multi-ink compatible all-in-one continuous printing

Silver conductive ink and NTC thermistor media can be processed in a single-device, switchable atomization module, eliminating the need for multi‑step changeovers and repeated substrate lamination steps.

• Digital rapid iteration, compatible with various chip heat sinks.

CAD allows direct modification of array pixel counts and electrode spacing, enabling rapid prototyping for server, industrial‑control, and consumer‑grade CPU coolers without the need to fabricate photomasks.

III. Five Key Technological Innovations

Innovation 1: Globally innovative fabrication of an aerosol‑direct‑write heat sink integrated with a two‑dimensional CPU thermal sensing array.

Innovation 2: A continuous serpentine printing process combined with mask‑cutting technology addresses the issue of uneven thermal‑sensitive layer thickness.

Innovation: 3 Low-Power Passive Matrix + Zero-Potential Scan Readout Architecture

Innovation 4: A Unified Global Polynomial Calibration Algorithm

Innovative 5-Hardware Thermal Fingerprint Security Recognition System

IV. Existing Process Challenges and Corresponding Solutions for Overcoming Them

Challenge 1: Metal heat sinks are conductive, making the sensing layer prone to short circuits; moreover, an excessively thick insulating film can impair heat dissipation.

Challenge 2: Intermittent on-off cycling of the aerosol leads to uneven thickness of the thermosensitive layer and significant pixel-to-pixel temperature variations.

Challenge 3: Cross‑printing multi‑layer electrodes is prone to misalignment, leading to failure of temperature‑sensing pixels.

Challenge 4: Crosstalk between rows and columns in conventional matrix circuits, leading to distorted temperature readings.

Challenge 5: Infrared temperature measurement can only perform short-term, offline monitoring and cannot provide 24/7 online operation.

V. Future Diversified Industrial Application Scenarios

1. Online Thermal Management for Data Center Server Clusters

2 Industrial Control / Military High-Performance Processor Security Monitoring

3 Laptop/Desktop Gaming CPU Cooling Optimization

4 Power Semiconductor IGBT and MOS Heat Dissipation Monitoring

5. Rapid Thermal Characterization Platform for Chip R&D Laboratories

Figure 1. a) Manufacturing process of the two-dimensional passive matrix‑printed sensor array: First, prior to fabricating the polyimide layer, the aluminum surface is ground and polished to achieve a smooth finish; this layer serves as both an electrical insulator and the printing substrate. Next, an aerosol jet printer is used to sequentially deposit all sensor layers from bottom to top: (1) the interconnect layer, (2) the bottom contact line layer, (3) the thermistor material layer, and (4) the top contact line layer. Each deposition step is followed by curing or sintering. b) Schematic illustration of the fully assembled sensor array, including a close-up view of a single sensor pixel composed of the individual deposited layers.

Figure 2. a) Schematic of the test setup, comprising a motherboard equipped with a CPU, a cooling unit, and an external control system. The sensor array is mounted upside down on the surface of the CPU chip after its cover has been removed. A photograph of the actual experimental apparatus is shown in Figure S2 (Supporting Information). b) The graph illustrates the nonlinear NTC response characteristics of three representative pixels as a function of temperature. Despite various measures taken to mitigate non-uniformities, each pixel still exhibits slightly different resistance values. c) The readout circuit measures the current under a 1 V bias; this current depends on the pixel’s resistance and is converted by an analog-to-digital converter (ADC). A calibration function can be established individually for each sensor pixel using a fourth-order polynomial. Overall, employing a unified average fitting function (shown as the black curve) yields more consistent results; to make this average function applicable to all pixels, a scaling factor is introduced. This calibration function is subsequently used to convert ADC readings into temperature values.

Figure 3. a) To provide a comprehensive view of the exposed CPU die, the stock heatsink has been removed. The Intel Core i9‑9900K processor used in this study features eight cores arranged in two opposing rows. Only the operational states of individual cores were examined [43]. b–d) These images illustrate the temperature evolution of the CPU under load. All images were captured without the CPU cooler: (b) shows the chip at idle; (c) reveals a localized hot spot that emerges immediately upon loading the second core; (d) depicts the thermal distribution when the second core remains under sustained load, with the blue box highlighting the region containing all eight cores. e–g) For comparison, these images also show the response of a printed‑type temperature‑sensor array when the second core is loaded. A marked difference is evident between (d) and (g): in (g), the thermal distribution remains confined to a single localized area.

Figure 4. a) As shown in the heat map, Core II is located on Line 8 (indicated by the red box). b) This figure illustrates the temporal evolution of temperature along Line 8. During the initial measurement phase, Core II remains stationary, and all pixels on Line 8 exhibit a uniform temperature distribution. Upon application of stress to Core II, the temperature rises immediately, with the increase concentrated primarily at the top of the loaded region and its corresponding locations. As the cooler regions begin to warm up, the temperature continues to climb. Finally, when Core II returns to a stationary state, the temperature decreases and recovers to a level similar to that observed prior to the stress.

Figure 5. (a–h) shows the temperature response curves of the printed sensor array for each individual CPU core under load. The right-hand panel presents the temperature distribution at the sensor pixels highlighted by red boxes. Overall, the measured temperature profiles closely match the core locations depicted in the official CPU layout shown in Figure 3a; the x‑ and y‑coordinates of the hotspots clearly delineate the specific positions of the individual cores.