I. Core Research Summary

• Chip-First Layer-by-Layer Conformal All-Additive Packaging Architecture

The bare die is mounted on a molybdenum–copper thermal‑matched substrate, and aerosol‑based printing is used to sequentially deposit a sloped transition layer, a high‑dielectric‑constant MIM capacitor dielectric, and RF microstrip lines, thereby directly fabricating a complete RF interconnect and filtering capacitance on the die surface, eliminating wire bonding and external chip‑mounted capacitors.

• In-situ mixed BaTiO₃/PI nanocomposite dielectric, integrating high-capacitance MIM capacitors.

Two aerosol streams atomize PI and barium titanate inks, respectively, enabling in-situ mixing and forming a high‑dielectric‑constant thin film during printing. The resulting equivalent dielectric constant is 7.1, with a maximum capacitance of 28.43 pF per cell—representing the highest capacitance in the industry for this type of aerosol‑based capacitor—and it can be used directly as a bypass filter in power amplifiers.

• Broadband, low-loss RF interconnects with performance comparable to bare chips.

At 5–20 GHz, the total package‑level insertion loss is less than 2.3 dB, with an average in‑band insertion loss of only 1.3 dB; the package delivers a maximum gain of 21.7 dB and a saturated output power of 21.9 dBm—performance that closely matches the manufacturer’s bare die specifications of 22 dB gain and 22 dBm saturation power, with virtually no degradation, significantly outperforming commercially available QFN packages.

• High and low temperature, power cycling—high reliability and stability.

After 1,000 power cycling cycles and seven high–low temperature shock tests at 200°C, the RF gain and output power variations remain below 0.32 dB, with no cracking of the dielectric layer and no delamination of the silver traces, thereby meeting the stringent reliability requirements of military‑grade RF applications.

• Single-device, multi-material monolithic molding; single‑package printing in just 100 minutes.

Pneumatic–ultrasonic dual‑atomization switching enables continuous printing of three types of inks—dielectric, high‑k composite, and conductive silver—eliminating the need for multiple lithography, coating, and chip‑mounting steps and boosting prototype‑iteration efficiency by 90%.

II. Complete Packaging Process Flow and Core Process Advantages for Aerosol Dispensing

(1) Complete Chip-First Microwave Package Fabrication Process

• Polishing of MoCu carrier substrates, silver‑epoxy bonding in a nitrogen atmosphere, and bare‑die GaAs power amplifier HMC451.
• A base coating adhesion promoter is applied, followed by pneumatic atomization of PI ink to print the base insulating layer.
• Dual-channel aerosol simultaneous injection of PI and BaTiO₃ nanoinks, followed by in-situ mixing to form a high‑dielectric‑constant thin film, is used to fabricate the dielectric layer of MIM capacitors.
• Print a 30°‑inclined PI fillet ramp to compensate for the height difference between the chip and the substrate, thereby achieving a smooth RF transition.
• Ultrasonic atomization of silver nano‑ink enables multi‑angle printing of 50‑Ω microstrip and GSG coplanar waveguide RF circuits.
• Segmented nitrogen‑based, stepped high‑temperature curing is applied to the dielectric and metal layers, completing an all‑additive, integrated power amplifier package.

(II) Five Major Process Advantages (Comparison of Gold Wire Bonding, LTCC, and Flip-Chip Technologies)

• Gold‑free, low‑parasitic interconnects significantly reduce high‑frequency losses.

The arched gold wire is eliminated, and the chip pads are directly conformally connected to the microstrip plane, thereby eliminating lead‑induced parasitic inductance and significantly improving millimeter‑wave impedance matching performance above 18 GHz.

• Multi-material in-situ composites, integrated bypass capacitors

The same device simultaneously blends high‑dielectric‑constant barium titanate with PI in real time, enabling direct in‑package molding of MIM filter capacitors and eliminating the need for chip mounting, pad fabrication, and reflow soldering, thereby reducing module size.

• Conformal printing with irregular height differences, perfectly matching chip steps.

Aerosol jet printing offers a safe nozzle-to‑substrate distance of 1–5 mm, enables rounded‑corner slopes on inclined surfaces, and provides smooth transitions across height differences of several hundred micrometers between the chip and the substrate—capabilities that conventional planar lithography cannot achieve.

• The thermal‑matching carrier board is designed for low‑temperature molding, ensuring no thermal damage to the chip.

The entire curing process operates at a maximum temperature of 295°C; when paired with a molybdenum–copper substrate featuring low thermal expansion, the GaAs chip avoids high‑temperature warping and performance degradation.

• Digital, maskless rapid iteration has sharply reduced R&D costs.

Simply modify the capacitor dimensions, microstrip line widths, and ramp‑profile CAD files to re‑tool; by contrast, LTCC ceramic tooling typically takes several weeks, whereas aerosol‑based prototyping can produce revised samples on the same day.

III. Five Core Technological Innovations of This Study

Innovation 1: The world’s first Chip-First aerosol microwave fully encapsulated process.

Innovation 2: Dual-Path In-Situ Mixing of Aerosol-Based High-Dielectric Nanocomposite Dielectrics

Innovation 3: Multi-Angle Rounded-Slope Conformal Interconnect Technology

Innovative 4‑channel broadband power amplifier integrated solution with no external capacitors

Innovative dual-loop verification of additive‑packaging reliability, incorporating both power and thermal metrics.

IV. Existing Process Challenges and Corresponding Solutions for Overcoming Them

Challenge 1: Gold wire bonding introduces parasitic inductance, leading to significant insertion loss and reduced bandwidth in the millimeter-wave frequency range.

Challenge 2: LTCC/PCB packaging requires discrete chip capacitors, resulting in a large module footprint and cumbersome assembly.

Challenge 3: There is a height difference of several hundred micrometers between the chip and the substrate, leading to easy breakage of RF traces and significant signal reflections.

Challenge 4: High‑dielectric barium titanate ink is difficult to uniformly blend with polymers, leading to delamination of the thin film.

Challenge 5: Traditional multi-layer packaging involves numerous processes and long lead times, resulting in slow product iteration.

V. Future Diversified Industrial Application Scenarios

• Airborne/Satellite Millimeter-Wave Power Amplifier Module

• Automotive 77 GHz Millimeter-Wave Radar Front-End

• 5G base station miniature RF transceiver chip

• Portable RF detection instrument

• Rapid Prototyping Platform for University RF Laboratories

Figure 1. (a) Exploded view of the packaging structure, illustrating the manufacturing process; (b) Cross-sectional view showing the layered material architecture.

Figure 2. Schematic diagrams of the package designs for two types of packaged components (Package 1 and Package 2), with dimensions in millimeters. The values in parentheses indicate the target material thicknesses: (a) polyimide (PI); (b) silver (Ag).

Figure 3. Capacitor configurations for the characterization of nanocomposites (dimensions in millimeters): (a) PI; (b) Ag

Figure 4. Schematic diagram of the AJP‑encapsulated 2× through‑hole design (dimensions in mm), corresponding to (a) the PI type and (b) the Ag type, respectively.

Table I: Measured Thickness of Printed Materials

Figure 5. Two fabricated package structures and one of the material characterization setups. (a) Bypass capacitor; (b) Packaged chip; (c) Perspective view of the package structures shown in (a) and (b); (d) Two-dimensional cross-sectional view; (e) Capacitor used for material characterization.

Figure 6. Measurement Setup Configuration

Figure 7. Measured capacitor parameters and extracted dielectric properties. Parasitic effects cause errors to increase with frequency. (a) Capacitance; (b) Dielectric constant εr; (c) Tan δ.

Table II: Comparison with State-of-the-Art AM Capacitors

Figure 8. Measured small-signal S-parameters of the AJP‑packaged chip, compared with those of the publicly available bare die [10] and a commercial off‑the‑shelf (COTS) packaged device [14]: (a) S11; (b) S12; (c) S22; (d) S21.

Figure 9: The 2x value obtained through measurement

Figure 10. Performance comparison between a package with doubled loss after layer removal and the bare die [10]

Figure 11. Large-signal load pull test results for AJP packages at an operating frequency of 8 GHz. (a) Package 1; (b) Package 2.

Table III: Comparison with Other AM Packages

Figure 12. Large-signal load pull test results of AJP packages at 9 GHz. (a) Package 1; (b) Package 2.

Figure 13. Large-signal load pull test results for AJP packages at a frequency of 10 GHz. (a) Package 1; (b) Package 2.

Figure 14. Large-signal load-pull test results for AJP packages at 11 GHz. (a) Package 1; (b) Package 2.

Figure 15. Deviations in performance as a function of power and temperature cycling. (a) Maximum gain; (b) Comparison of the initial gain measurement with the gain after 1,000 power cycles and after one, three, and seven temperature cycles.