I. Abstract of the Paper’s Core Research

This study prepares high-purity graphene ink suitable for aerosol jet printing and employs the TLM transmission-line method to characterize the electrical properties of graphene interconnects across varying numbers of printed layers and on different substrates. Complementary analyses—including infrared thermography, electrical breakdown testing, and finite-element simulations—are used to elucidate Joule‑heat dissipation and failure mechanisms. The key findings are as follows:

Graphene ink specially formulated for high- and low-defect aerosols

Graphene flakes were prepared via liquid-phase exfoliation, with an ink concentration of 3.5 mg/mL, an ID/IG ratio of only 0.24, and a flake size of approximately 80 nm. The defect density is significantly lower than that of conventionally printed graphene, and the atomization is stable, with no agglomeration or nozzle clogging.

Precise control of the number of printed layers to tune electrical conductivity.

With 5–50 printing cycles, the film thickness increases linearly, and its electrical conductivity improves accordingly. At 50 layers, the graphene exhibits a sheet resistance as low as 1.5 kΩ/sq, with electrical conductivity 30 times higher than that of a 5-layer sample, and its charge transport follows the variable-range hopping (VRH) model.

Differences in base thermal resistance lead to significant disparities in heat dissipation.

The total thermal resistance of the alumina substrate is only 185 K/W, compared to 350 K/W for the silicon substrate and as high as 9,285 K/W for the Kapton flexible substrate; the breakdown current density of the alumina substrate is ten times that of the flexible substrate, while polymer substrates are highly prone to failure due to high‑temperature melting.

Complete Electromagnetic–Thermal Coupled Analysis System

A lumped thermal resistance model, ΔT = P × R_TH, was established to decompose the thermal resistance into three layers: the graphene bulk, the interface, and the substrate. Infrared thermometry, combined with COMSOL simulations, was used to reproduce the temperature‑rise distribution along the circuit, confirming that the internal pores in the printed graphene are the primary source of thermal resistance.

Failure Mechanisms of Two Typical Types of Line Breakdown

Hard ceramic substrate: graphene oxidation leads to filament breakage at high temperatures; flexible Kapton substrate: the substrate melts prematurely, damaging the circuitry; cross-sectional TEM confirms that 15% porosity in the film causes internal gases to expand upon heating, resulting in characteristic cracks aligned parallel to the current flow.

II. Complete Preparation Procedure for Aerosol‑Based Graphene Interconnections

1) Graphene flakes were prepared via liquid-phase exfoliation of graphite, using ethyl cellulose as a stabilizer and a cyclohexanone/terpineol mixed solvent to formulate an ink at a concentration of 3.5 mg/mL.

2) Optomec AJ300 aerosol deposition system, utilizing ultrasonic atomization and precise control of nitrogen carrier and sheath gas ratios, with the substrate maintained at a constant 65°C to accelerate solvent evaporation.

3) Print the TLM standard test pattern on three types of substrates—Kapton, SiO₂/Si, and Al₂O₃—at 5, 10, 20, 30, and 50 layers.

4) Stepwise low-temperature baking followed by 250°C isothermal annealing to remove polymeric additives, then evaporation deposition of silver contact electrodes;

5) Comprehensive characterization, including four-probe electrical measurements, infrared thermography, TEM cross-sectional analysis, COMSOL multiphysics thermal simulations, and breakdown voltage testing.

III. Five Core Process Advantages of Aerosol-Generated Graphene

Film thickness is linearly and precisely controllable, and electrical conductivity can be adjusted on demand.

By precisely controlling the number of printing passes, the film thickness can be accurately tuned without the need to change inks, enabling a single set of equipment to fabricate both high‑resistance sensing circuits and low‑resistance, high‑power circuits.

Maskless micron-scale high-precision patterning

The single‑track printing line width is approximately 50 μm, enabling the fabrication of interdigitated, microstrip, and TLM precision test structures, suitable for miniaturized chip interconnections.

Multi-substrate compatible, rigid / Universal for flexible substrates

Aluminum oxide, silicon wafers, and polyimide flexible films can all be stably deposited, meeting the requirements of both high-temperature devices and wearable electronics.

Gentle low-temperature forming results in minimal damage to graphene crystals.

The material undergoes heat treatment at temperatures below 250°C throughout the entire process, fully preserving its two-dimensional layered structure, with an extremely low defect density and outstanding electrical conductivity.

Site-specific deposition saves graphene raw materials.

The aerosol-focused beam deposits material exclusively within the target area, significantly reducing the waste of costly carbon nanomaterials compared to conventional spin coating.

IV. Five Core Technological Innovations of This Study

Innovation 1: An Integrated Characterization System for Aerosol‑Graphene Electrical and Thermal Dissipation Properties

The system quantifies the Joule‑heating dissipation, thermal resistance, and breakdown characteristics of AJP‑fabricated graphene interconnects, thereby filling a critical gap in the thermal design theory for printed carbon‑based circuits.

Innovative Two-Layer Lumped Thermal Resistance Analytical Model

By decomposing the thermal resistance contributions of graphene’s bulk, interface, and substrate, this approach quantitatively isolates the substrate’s decisive role in heat dissipation, providing a computational tool for thermal design of circuitry.

Innovation 3: Number of Printing Layers – Quantitative Correlation with Electrical Conductivity

Establish a comprehensive electrical conductivity database spanning 5 to 50 layers, enabling rapid matching of printing process parameters based on the target resistance.

Innovation 4: Unveiling the Differentiated Failure Mechanisms of Two Types of Substrates

Distinguish the distinct ablation modes of flexible polymers and ceramic substrates, and elucidate the underlying mechanisms responsible for the characteristic failure morphology characterized by parallel cracks induced by pore expansion.

Innovative 5-Infrared Imaging + Finite Element Co-Simulation Verification Scheme

The measured temperature rise closely matches the COMSOL simulation, enabling early prediction of hotspots in high-power circuits and shortening the device iteration cycle.

V. Current Industry Challenges and Corresponding Solutions

Challenge 1: Graphene‑based printed circuits lack thermal performance data, making them prone to overheating and burnout in high‑power applications.

✅ Comprehensive thermal resistance and breakdown power database, enabling proactive assessment of substrate thermal limits and mitigating the risk of high-temperature failure.

Challenge 2: There is no unified design rationale for the performance of graphene circuits on different substrates, and the fabrication process relies entirely on trial-and-error.

✅Establish two sets of quantitative criteria—resistance and thermal resistance—for layer count, enabling rapid alignment with device application scenarios.

Challenge 3: The flexible PI substrate has extremely poor thermal conductivity, leading to significant temperature rise in high-current circuits.

✅The study clearly defines the upper limit of current on flexible substrates and proposes an optimized thermal management strategy involving layered thinning and localized ceramic reinforcement.

Challenge 4: The internal pore structure of printed graphene remains unknown, and the thermal conduction mechanism is not yet fully understood.

✅ TEM analysis reveals a 15% porosity, elucidating the core mechanism by which pore enlargement increases the thermal resistance of the film and guiding improvements to the densification process.

Challenge 5: Lack of electro‑thermal coupling simulation tools, resulting in high prototype testing costs.

✅ Provides reusable COMSOL thermal simulation models, enabling computers to predict hotspots in advance and reduce the need for sample preparation.

VI. Future Diversified Industrial Application Scenarios

1 Wearable Flexible Conductive Sensing Circuitry

Low-power graphene sensing electrode, compatible with a Kapton flexible substrate, for low-current physiological monitoring patches.

2 Miniature RF Antennas and Chip-Level Micro-Interconnections

Alumina‑based, highly conductive graphene microstrip, capable of withstanding high currents, for internal wiring in miniature wireless modules.

3 Micro-joule heating element

High-precision aerosol‑patterned heating resistors, miniature temperature‑control chips, and thermal sources for trace‑gas sensors.

4 Aerospace Lightweight Carbon-Based Circuitry

High-temperature‑resistant graphene circuits on silicon/ceramic substrates, enabling lightweight airborne sensing electronics.

5 Laboratory Carbon-Based Electronics R&D Platform

Rapidly print graphene samples of varying thicknesses, simultaneously measure their electrical conductivity and thermal management properties, and accelerate the iteration of new materials.

Image and Text Guide

Figure 1. Preparation and characterization of AJP graphene ink

Figure 2. AJP graphene interconnect TLM test structure and SEM morphology

Figure 3. Scaling laws of geometric and electrical dimensions as a function of the number of printing passes.

Figure 4. Power consumption, IR thermography, COMSOL simulation, and electrical breakdown on three types of substrates.

Figure 5. Cross-sectional TEM porosity versus breakdown SEM morphology