I. Abstract of the Paper’s Core Research

• 1D carbon nanotube + 2D h-BN heterostructure transistor architecture

One-dimensional semiconductor carbon nanotubes form the conductive channel, while two-dimensional hexagonal boron nitride serves as an ultrathin gate insulator; silver nanowires are used as the source–drain and top-gate electrodes. All three materials are fabricated via aerosol jet printing, enabling the realization of a top-gate‑type flexible thin‑film transistor.

• Industry’s lowest-temperature complete manufacturing process

The end-to-end platform maintains a maximum constant temperature of only 80°C, eliminating the need for high-temperature annealing. In contrast to conventional carbon‑nanotube transistor processes that typically require high‑temperature steps between 120–200°C, this approach is compatible with thermally sensitive, low-cost substrates such as Kapton polyimide and standard printing paper.

Excellent electrical performance: an optimal mobility of 10.7 cm²/V·s, a maximum on-off ratio of 3.5×10⁵, a low subthreshold swing, and minimal gate‑voltage hysteresis; the h‑BN film exhibits a stable dielectric constant of approximately 3.01, with gate leakage current approaching the noise level.

• Ultra-strong mechanical bending stability

Under a bending radius of 3 mm (with 2.1% strain), the device underwent 1,000 cyclic tests without any noticeable degradation in its transfer characteristics; calculations indicate that an ultra-thin substrate as thin as 25 μm can support an extremely small bending radius of 0.4 mm, making it well suited for stretchable electronics.

• In-situ rinsing replaces external wet processing.

The carbon‑nanotube layers do not require removal from the equipment for soaking and cleaning; a brief in‑situ rinse with toluene on the platform is sufficient to remove surface dispersants, yielding device performance comparable to that of conventional bath‑washing protocols while significantly streamlining automated production‑line workflows.

• h-BN dielectrics require no thermal treatment to enhance performance.

Verification shows that 150°C annealing induces only a transient threshold shift, with no improvement in long-term electrical performance, thereby eliminating the high-temperature curing step for the insulating layer and further reducing energy consumption and the risk of substrate damage.

II. Core Operating Principle of Aerosol Spraying & Unique Process Advantages

(1) Complete In-Situ Printing Process Flow

• The substrate is surface‑activated with polylysine and remains firmly attached to the print platform throughout the entire printing process without being removed.
• Aerosol printing is used to fabricate semiconductor carbon nanotube channels, followed by in-situ toluene rinsing at 80°C on the platform to remove surface polymer dispersants.
• Using the same equipment, sequentially deposit the source and drain electrodes made of silver nanowires, the two-dimensional h‑BN insulating dielectric, and the top-gate silver electrode.
• After each layer is printed, the build platform undergoes low-temperature drying; the entire process is fully enclosed and continuous, with no part‑turning or external operations.

(II) Five Core Technological Advantages (Compared with Inkjet, Screen Printing, and Spin Coating)

• In-situ integrated printing, with no need to remove the sample throughout the entire process.

In other printing processes, each layer requires removing the substrate for cleaning and drying, which introduces contamination and alignment errors; in contrast, aerosol-based layered continuous deposition enables automated closed-loop production, significantly improving yield.

• Wide ink compatibility; universal for 1D/2D and metallic nanomaterials.

A single system can stably atomize three types of aqueous inks with vastly different physical properties—carbon nanotubes, water‑based h‑BN, and silver nanowires—without requiring replacement of the atomization core, thereby halving the capital investment in production equipment.

• Sheath‑gas isolation prevents nozzle clogging and is compatible with water‑based two‑dimensional inks.

Conventional inkjet printing is prone to nozzle clogging by nanosheets; in contrast, aerosol‑coaxial sheath technology isolates the ink from the nozzle wall, enabling long‑term continuous printing without filament breakage or image defects.

• Ultra-low-temperature process, compatible with paper-based and ultra-thin plastic substrates.

The maximum processing temperature is only 80°C, ensuring that standard office paper and ultra-thin flexible films do not undergo thermal deformation, thereby enabling low-cost, disposable paper-based sensor circuits.

• High-precision maskless direct writing with micron-scale channel controllability.

CAD‑customized transistor layout, with channel length and dielectric thickness linearly tunable via the number of printed layers—no lithography or etching required, enabling rapid iteration for small‑batch production.

III. Key Technological Innovations of This Study

Innovation 1: Innovative fabrication of a 1D carbon nanotube–2D h-BN all-aerosol‑grown composite transistor architecture.

Innovative 2 HPMC binder ink formulation addresses the challenge of multilayer mutual solubility.

Innovative in-situ carbon nanotube rinsing process on Platform 3

Innovation 4 confirms that h-BN dielectrics do not require high-temperature curing.

Innovative Five Feasible Solutions for Ultra-Low-Temperature Paper-Based Circuits

IV. Existing Process Challenges and Corresponding Solutions for Overcoming Them

Challenge 1: Water-based multilayer inks tend to be mutually soluble upon stacking, leading to interfacial mixing and a sharp increase in leakage current.

Challenge 2: Residual dispersant in carbon nanotube films leads to reduced carrier mobility.

Challenge 3: Two-dimensional h-BN ink tends to clog micro‑nozzles, making long‑term mass production impractical.

Challenge 4: High-temperature processing limits the use of low-cost, thermally sensitive flexible substrates.

Challenge 5: Cracking of the thin film after bending and a significant drop in current.

V. Future Diversified Industrial Application Scenarios

1. Paper-based disposable IoT sensing tag

2. Flexible Electronic Skin and Wearable Sensors

3. Flexible Display Driver Backplane

4. Intelligent Electronic Circuits for Textiles

5. Specialized Lightweight Measurement and Control Chip

Figure 1. Bendable, fully in‑situ printed 1D–2D thin‑film transistors (steps II–VI do not require removing the substrate from the printing platform). (a) Schematic of the fabrication process, including: (I) functionalization of the substrate with poly‑L‑lysine (PLL); (II) printing of carbon nanotube (CNT) channels; (III) cleaning of the CNT channel film; (IV) printing of silver nanowire (AgNW) source/drain (S/D) electrodes; (V) printing of an h‑BN gate dielectric layer; (VI) printing of AgNW gate electrodes. (b) and (c) show, respectively, a photograph and an optical image of the finished thin‑film transistor. (d) shows an atomic force microscopy image of the printed CNT channel after cleaning.

Figure 2. Fully printed h‑BN capacitor structure. (a, b) Photographs of the printed AgNW/h‑BN/AgNW heterostructure, with colored dots indicating the locations where the SEM images were acquired. (c) Schematic illustrating the cross‑section of the printed stacked structure and the corresponding SEM imaging positions. (d, e) Top‑view SEM images of an h‑BN film directly printed on a SiO₂/Si substrate, revealing individual h‑BN flakes; (f) and (g, h) show, respectively, the cross‑section and top‑view SEM images of an AgNW film directly printed on a SiO₂/Si substrate; (i) and (j, k) present the cross‑section and top‑view SEM images of the AgNW/h‑BN/AgNW stacked structure.

Figure 3. Dielectric properties of h‑BN thin films fabricated by aerosol jet printing. (a) Schematic illustration of the capacitor structure. (b) Frequency-dependent small-signal capacitance per unit area of gold/h‑BN/silver nanowire capacitors as a function of dielectric layer thickness, which is determined by the number of printing passes. A DC bias of 2 V is applied, with a superimposed 50 mV AC signal. (c) Linear fit between the reciprocal of the printed h‑BN dielectric layer thickness and the corresponding film capacitance. Each capacitance value represents the average of three measurements, with error bars indicating the standard deviation; dielectric layer thicknesses were determined using profilometry as shown in Figure S6.

Figure 4. Electrical performance of fully printed 1D–2D thin-film transistors (TFTs). (a) Transfer characteristics (solid line) and subthreshold characteristics (dashed line) of a printed 1D–2D TFT subjected to external rinsing; (b) Output characteristics of the same device as in (a); (c) Comparison of transfer characteristics (solid line) and subthreshold characteristics (dashed line) between 1D–2D TFTs treated by in-situ rinsing and those treated by external rinsing.

Figure 5. Flexibility test results for printed 1D–2D thin-film transistors. The figure shows the subthreshold characteristics of the device under the following conditions: (a) when bent at different bending radii; (b) after multiple bending cycles (with a bending radius of 3 mm and a strain of approximately 2.1%); and (c) the relationship between strain and bending radius for substrates of varying thicknesses. The green dashed line indicates the strain value for the 127-μm-thick substrate used in this study at a bending radius of 2 mm. The inset shows a photograph of the printed 1D–2D thin-film transistor at a bending radius of 3 mm.

Figure 6. Performance comparison between one-dimensional and two-dimensional thin-film transistors (TFTs) and previously reported printed flexible carbon nanotube thin-film transistors (CNT‑TFTs). The comparisons include: maximum processing temperature, (a) effective hole mobility, and (b) on/off current ratio. Diamond symbols denote average values or typical results, while circle symbols indicate the best reported results.