I. Abstract of the Paper’s Core Research

• Ultra-low power performance to the extreme

The CMOS inverter operates at a minimum supply voltage of only 0.2 V, with a per‑unit‑area power consumption as low as 0.0124 pW/μm, and a single‑gate dynamic power dissipation of just 6.2 pW. It delivers a voltage gain exceeding 11, a noise margin of up to 75% of VDD, and achieves rail‑to‑rail full‑logic output.

• Top-tier radiation resistance

The device can withstand a high‑dose irradiation of 365 rad/s, with a total ionizing dose (TID) exceeding 2 Mrad—far surpassing that of commercial radiation‑hardened silicon chips (~1 Mrad). Only the N‑channel transistors exhibit irradiation‑induced degradation due to the epoxy‑doped layer, while the P‑channel transistors show virtually no performance variation.

• All-Print Eco-Friendly Flexible System

The substrate is made of biodegradable paper, paired with an ultra-thin 4.2-nm aluminum oxide gate dielectric, aerosol-printed carbon nanotube channels, and screen-printed silver electrodes; it retains stable logic characteristics even after 10,000 bending cycles and 30 days of storage.

• Process is controllable and adjustable.

By precisely controlling the number of printed layers of aerosol‑dispersed carbon nanotubes, the threshold voltage and mobility can be accurately tuned; three printing cycles yield the optimal process, with a mobility reaching 15.7 cm²V⁻¹s⁻¹. Selective doping using an epoxy‑amine ink enables conversion from p‑type to n‑type, facilitating symmetric CMOS pairing.

• Complete logic device verification

A stable NAND gate has been successfully fabricated, with clearly distinguishable high and low logic levels, demonstrating that aerosol‑printed paper‑based circuits can be used to construct complex, low‑power integrated systems.

II. Unique Advantages of Aerosol Jet Printing in Fabricating Electronic Devices

(1) Core Workflow of Aerosol Spraying

(II) Five Key Advantages Over Traditional Craftsmanship

• Compatible with lightweight, porous paper substrates

Spin coating and thermal evaporation can easily damage the porous structure of paper; aerosol deposition, being non-contact and performed at a distance, avoids compressing or damaging the paper and is fully compatible with biodegradable flexible substrates.

• Uniform and controllable carbon nanotube films

It enables precise control over the number of printed layers, flexible adjustment of channel carbon‑nanotube density, and accurate matching of threshold‑voltage requirements, while ensuring that the thin film is free from agglomeration and large‑area defects.

• Maskless digital fabrication, high-precision microcircuit printing

CAD‑customized pixel circuits with micron‑scale channel direct patterning eliminate costly processes such as photolithography and mask fabrication, thereby streamlining the paper‑based electronic manufacturing workflow.

• Compatible with wide-viscosity inks

Carbon nanotube dispersions, doped inks, and conductive silver pastes can all be used with a single printing system, enabling the stepwise, integrated fabrication of multilayer functional films.

• Low material loss, suitable for flexible roll-to-roll mass production.

Directional droplet deposition yields ink utilization far exceeding that of spin coating; when paired with paper substrates, it enables the development of low-cost, recyclable printed electronics production lines.

III. Key Technological Innovations of This Study

Innovation 1: Paper-based ultrathin aluminum oxide gate dielectric structure with low leakage

Innovation 2: Precise Control of Aerosol Layer Count to Tune Carbon Nanotube Transport Properties

Innovation 3: Selective epoxy doping enables symmetric E‑type CMOS.

Innovation 4: A synergistic radiation-resistant system combining paper-based and ultra-thin dielectric materials

Innovation 5: Fully Printed, Biodegradable, Ultra-Low-Power CMOS Complete Solution

IV. Existing Process Challenges and Corresponding Solutions for Overcoming Them

Challenge 1: The ultra-thin aluminum oxide dielectric suffers from severe leakage, leading to increased device power consumption.

Challenge 2: Single-walled carbon nanotube films can only achieve p-type conductivity, making it difficult to fabricate CMOS circuits.

Challenge 3: With too few layers, migration is low; with too many layers, off-state leakage increases.

Challenge 4: Rapid Performance Degradation of N‑type Transistors After Irradiation

Challenge 5: After multiple bending cycles, the interfacial contact between the silver and carbon nanotube deteriorates.

V. Future Diverse Application Scenarios

1. Aerospace Deep-Space Exploration Electronic Equipment

2. Polar / Deep-Sea Extreme Environment Monitoring Sensors

3. Disposable IoT Paper-Based Sensing Label

4. Wearable Flexible Medical Monitoring Devices

5. Nuclear Industry Radiation Environment Monitoring and Control Chip

Figure 1. Structure and characterization of paper-based carbon nanotube thin-film transistors (CNT TFTs): a) CNT TFT array on a paper substrate; b) Optical image of the CNT channel film under an ultra-thin AlOX dielectric layer, with channel dimensions L = 170 µm and W = 500 µm; c) Schematic diagrams of P‑type and N‑type CNT TFTs; d) Transfer characteristics of printed E‑type P‑type and f) E‑type N‑type CNT TFTs at VDS values of −0.25 V and 0.25 V, respectively; g) Schematic illustrating the location of the resin film in screen-printed silver paste and the coordination bonds between silver ions and carboxyl groups; h) Transfer curves as a function of the number of CNT ink printing cycles; and i) the relationship between VTH values, µFE values, and j) SS values and the number of CNT ink printing cycles. (In figures i and j, the three circular markers indicate the optimal performance after three printing cycles; the lines are provided solely for visual guidance and do not represent specific models.)

Figure 2. Paper-based printed carbon nanotube CMOS thin-film transistors: a) Transfer characteristics of a P‑type TFT before polarity reversal (P‑type, printed three times), after polarity reversal (blue curve), and of a P‑type TFT printed twice; b) Output characteristics (with VGS step changes of ±0.2 V); c) Transfer characteristics of E‑type, P‑type, and N‑type carbon nanotube TFTs; d) Distribution of VTH, ION/IOFF, and hysteresis for 21 P‑type TFTs; e) Data for the N‑type TFTs shown in panel c (values represent averages, with Lorentzian distributions); f) Performance of a P‑type carbon nanotube TFT under 7,200‑second bias stress (VGS = −1 V, VDS = −0.25 V); g) Performance of an N‑type carbon nanotube TFT under 7,200‑second bias stress (VGS = 1 V, VDS = 0.25 V); h) Transfer characteristics of P‑type and i) N‑type carbon nanotube TFTs before and after 10,000 bending cycles. All transfer curves were measured at VDS = −0.25 V (for P‑type) or VDS = 0.25 V (for N‑type). Reference number: 15214095, published on June 11, 2022, downloaded from the Wiley Online Library via the Egyptian National Science and Technology Network (Enstinet) at https://onlinelibrary.wiley.com/doi/10.1002/adma.202204066. See the glossary for further details.

Figure 3. a) Output voltage characteristics of the inverter as a function of input voltage, ranging from 0.2 to 0.6 V; b) Power‑consumption curves corresponding to different VDD values (0.2–0.6 V); c) Comparison with previously reported power‑consumption data for CMOS inverters (lines are schematic and do not represent specific models); d) Variation of power consumption per unit length with input voltage; e) Schematic diagram and photograph of the NAND logic gate connection; f) Connection structure on a paper substrate; g) Output waveform of the NAND logic gate, with Vin and Vout set at 0 V and 1.5 V, respectively, representing logic “0” and “1”.

Figure 4. Radiation-hardening characteristics of carbon nanotube thin-film transistors (CNT TFTs) and CMOS inverters. a) Schematic illustration of the radiation effects in a CMOS inverter (the red‑marked excess positive charges in the N‑type TFT originate from commercial epoxy resin, while the blue‑marked native positive charges in the P‑type TFT arise from Co‑60 irradiation); b) Transfer characteristics of a P‑type CNT TFT fabricated on a paper substrate under VDS = −0.25 V and at various total ionizing doses (TID); c) Dependence of the threshold voltage (VTH) and the current ratio ION/IOFF on TID for the P‑type CNT TFT (lines are provided for reference only and do not correspond to any theoretical model); d) Transfer characteristics of an N‑type TFT under VDS = 0.25 V and at different TIDs; e) Dependence of VTH and ION/IOFF on TID for the N‑type CNT TFT (lines are for reference only and do not represent any theoretical model); f) Current–voltage characteristics of a CMOS inverter fabricated using a 0.5 V supply voltage (VDD) at various TIDs; g) Calculated voltage gain values of the CMOS inverter at different TIDs under VDD = 0.5 V.