I. Core Research Abstract

• Integrated molding of a double-layer conformal aerosol microwave circuit

Pneumatic atomization is used to print the SU‑8 dielectric layer at 30 μm, while ultrasonic atomization deposits silver ink directly to form a 70‑μm‑wide standard 50 Ω signal trace. Infrared laser local sintering boosts the electrical conductivity of the silver film to 1.7 × 10⁷ S/m, enabling maskless, single‑step fabrication of microstrip lines.

• High-frequency transmission loss is significantly superior to that of gold wire bonding.

2-mm standard transmission line with a standalone PCB structure: at 18 GHz, insertion loss is only 0.3 dB/mm; the transition structure to the MMIC chip exhibits 0.9 dB/mm loss at 18 GHz. By contrast, gold‑wire bonding of the same length results in over 4.8 dB loss at 18 GHz, with the S11 reflection coefficient degrading to −4.7 dB, whereas the aerosol‑based interconnect maintains stable impedance matching across the entire frequency band.

• Chip Height-Gradient–Adaptive Conformal Printing Process

For a 520-μm-thick silicon chip, an aerosol‑based layered SU‑8 dielectric is used to construct a sloped transition layer, seamlessly bridging the PCB ground plane and the chip’s solder pads, thereby eliminating stepped RF discontinuities. GSG narrow‑pitch pads with a 150-μm pitch are precisely aligned.

• Lithography-free digital rapid-iteration packaging and interconnects

CAD allows direct modification of trace width, dielectric thickness, and transition ramp dimensions, eliminating the need for tooling; a new RF package prototype can be completed in just two hours, making it ideal for rapid multi‑band MMIC validation.

• Wideband Stable Impedance Matching (50 Ω Standard)

HFSS simulation verifies that the curved surface SU—without compromising the microstrip impedance characteristics—yields measured S11 values below −13 dB across the entire frequency band, with no resonant spurious responses, thereby meeting the packaging requirements of wideband RF transceiver chips.

II. Complete Preparation Process Flow and Core Process Advantages of Aerosol Spraying

(1) Complete Microwave Microstrip Line Fabrication Process

• FR4 copper-clad laminate substrate cleaning, with the copper layer serving as a common ground plane;
• Pneumatic atomization is used to dilute the SU‑8 photoresist ink, and multi-layer printing creates a 30 μm insulating layer, followed by pre-baking at 150 °C and UV crosslinking curing.
• Ultrasonic atomization of silver‑nanoparticle conductive ink, CNC printing of 70‑μm microstrip signal traces, with low‑temperature pre‑drying at 60°C.
• 832 nm infrared laser localized sintering of silver traces, enhancing densification and reducing sheet resistance;
• Laser milling is used to form grooves for mounting the MMIC chip, followed by another aerosol‑printing step to deposit a sloped dielectric layer and interconnect silver traces, thereby completing the integrated RF path between the chip and its package.

(II) Five Major Process Advantages (Comparison of Gold Wire Bonding, Flip Chip, and Screen Printing)

• Eliminates lead parasitic inductance, offering high-frequency, low-loss performance.

With a suspended‑metal‑free structure and a planar, continuous conductive path, it completely eliminates the high‑frequency impedance mismatch caused by 1 nH/mm lead inductance, resulting in a substantial improvement in millimeter‑wave performance up to 18 GHz.

• Conformal deposition with height differences for irregular shapes, enabling seamless interconnection of chip slopes.

Aerosol with a safe spray distance of 1–5 mm enables layer-by-layer printing of graded dielectrics between the chip and the PCB step, naturally forming a smooth microwave transition structure. Conventional bonding cannot accommodate continuous traces with height differences.

• Micron-level high-precision narrow linewidth patterning (10 μm resolution)

Precisely compatible with 150-μm‑pitch chip pads, screen printing’s minimum line width of 100 μm falls short of meeting the demands of high‑density MMIC packaging.

• Dual-ink synchronous integrated printing, enabling one-step formation of both the dielectric and conductive layers.

The pneumatic and ultrasonic atomization modules can be switched on a single device, and the insulating layer and RF signal lines are processed continuously, eliminating the need for multiple complex steps such as coating, lithography, and etching.

• Low-cost rapid prototyping, with no consumption of precious-metal gold wire.

Silver ink is deposited only in the circuit areas, eliminating the need for large quantities of gold consumables; no custom intermediate lithography masks are required, shortening the new‑product packaging and iteration cycle by 80%.

III. Five Key Technological Innovations

Innovation 1: A novel microwave interconnect process integrating conductive and dielectric dual-layer media

Innovative 2-Surface SU-8 Dielectric Impedance–Controllable Design

Innovative Three-Stage Conformal Transition RF Path Solution

Innovative 4-Laser Local Low-Temperature Sintering Silver Circuit System

Innovative Standardized Process for Broadband Universal Aerosol Encapsulation

IV. Existing Process Challenges and Corresponding Solutions for Overcoming Them

Challenge 1: The parasitic inductance of gold wire bonding is significant, causing a sharp increase in loss at frequencies above 10 GHz.

Challenge 2: There is a height difference of several hundred micrometers between the chip and the PCB, which can easily cause reflection-induced clutter in microwave transitions.

Challenge 3: Traditional lithography-based flip-chip interposers are costly and have long fabrication lead times.

Challenge 4: The wide line width of screen printing cannot accommodate the high-density, fine-pitch MMIC pads.

Challenge 5: High-temperature sintering of the silver film can easily damage the chip and the organic packaging substrate.

V. Future Diversified Industrial Application Scenarios

• Mass Production Packaging of Automotive Millimeter-Wave Radar MMICs

• 5G/6G RF Front-End Chip Packaging

• Satellite and aerospace high-frequency RF components

• High-frequency chip carrier for test and measurement instruments

• Rapid Prototyping of RF Chips in the Laboratory

Figure 1: Schematic diagram of a printed transmission line concept within a QFN package, intended for high-frequency applications as an alternative to wire bonding. The QFN thermal pad serves as the ground plane, while the MSL connects the silicon MMIC to the QFN package pins.

Table I: Summary of Dimensions Used in HFSS Simulations of Microstrip Lines

Figure 2: HFSS simulation design for a microstrip line with a curved dielectric topology.

Figure 3: HFSS simulation results for S21 and S11 in a microstrip line employing both curved-surface and planar topologies.

Figure 4: Schematic cross-section of an aerosol jet printing head

Figure 5: (a) Microscopic image of a printed transmission-line prototype on a printed circuit board, showing the ground plane (GND) and the transmission line (TL); (b) Microscopic images of the chip and the printed transmission line on the printed circuit board.

Figure 6: Cross-sectional schematic of the transition structure from the printed transmission line to the MMIC chip.

Figure 7: (a) Simulated and measured values of the 2‑mm‑long printed transmission line on the PCB, showing (a) the S21 parameter and (b) the S11 parameter; (c) the measured S21 parameter and (d) the measured S11 parameter for the chip connected via the printed transmission line.

Table II: Comparison of Published Printed Transmission Lines

Figure 8: Microscopic image of the chip (left) and an enlarged view of the transmission line integrated on the chip (right).

Figure 9: (a) Transmission line on a CMOS chip, showing the ground plane (GND) and the transmission line (TL); (b) Cross-sectional schematic.

Figure 10: (a) Measured S21 values of the transmission line on the chip; (b) Measured S11 and S22 values of the transmission line on the chip.

Figure 11: Measured S21 parameters of the printed transmission line and the measured S21 parameters of the wire-bonded structure.

Figure 12: Measured S11 parameters of the printed transmission line and the measured S11 parameters of the wire-bonded structure.